Verilog code for 3 to 8 Decoder - 74x138

 Gate Level Modelling:

	module ic74x138(G1, G2A_L,G2B_L,C,B,A,Y_L);
	input G1, G2A_L,G2B_L,C,B,A;
	output [0:7] Y_L;
	wire E,Abar,Bbar,Cbar;
	and a1(E,G1,~G2A_L,~G2B_L);
	not n1(Abar,A);
	not n2(Bbar,B);
	not n3(Cbar,C);
	nand na1(Y_L[0],Cbar,Bbar,Abar,E);
	nand na2(Y_L[1],Cbar,Bbar,A,E);
	nand na3(Y_L[2],Cbar,B,Abar,E);
	nand na4(Y_L[3],Cbar,B,A,E);
	nand na5(Y_L[4],C,Bbar,Abar,E);
	nand na6(Y_L[5],C,Bbar,A,E);
	nand na7(Y_L[6],C,B,Abar,E);
	nand na8(Y_L[7],C,B,A,E);
	endmodule

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 Data Flow Modelling:

	module ic74x138(G1, G2A_L,G2B_L,C,B,A,Y_L);
	input G1, G2A_L,G2B_L,C,B,A;
	output [0:7] Y_L;
	wire E;
	assign E = G1 & ~G2A_L & ~G2B_L;
	assign Y_L[0] = ~(~C & ~B & ~A & E),
	Y_L[1] = ~(~C & ~B & A & E),
	Y_L[2] = ~(~C & B & ~A & E),
	Y_L[3] = ~(~C & B & A & E),
	Y_L[4] = ~(C & ~B & ~A & E),
	Y_L[5] = ~(C & ~B & A & E),
	Y_L[6] = ~(C & B & ~A & E),
	Y_L[7] = ~(C & B & A & E);
	endmodule

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Behavioural Modelling:

	module ic74x138(G1, G2A_L,G2B_L,C,B,A,Y_L);
	input G1, G2A_L,G2B_L,C,B,A;
	output [0:7] Y_L;
	reg [0:7] Y_L;
	always@( G1, G2A_L, G2B_L,C,B,A)
	begin
	if (G1 & ~G2A_L & ~G2B_L)
	case({C,B,A})
	0: Y_L = 8'b01111111;
	1: Y_L = 8'b10111111;
	2: Y_L = 8'b11011111;
	3: Y_L = 8'b11101111;
	4: Y_L = 8'b11110111;
	5: Y_L = 8'b11111011;
	6: Y_L = 8'b11111101;
	7: Y_L = 8'b11111110;
	default: Y_L = 8'b11111111;
	endcase
	else
	Y_L = 8'b11111111;
	end
	endmodule

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