Verilog code for 8x1 Multiplexer - 74x151 and 1x4 Dual Demultiplexer - 74x155

  8x1 Multiplexer - 74x151 :

	module ic74x151(E, S, D, Y, Ybar);
	input E;
	input [2:0] S;
	input [0:7] D;
	output reg Y, Ybar;
	always@(*)
	begin
	if (E == 0)
	case (S)
	3'b000: begin Y= D[0]; Ybar = ~D[0]; end
	3'b001: begin Y= D[1]; Ybar = ~D[1]; end
	3'b010: begin Y= D[2]; Ybar = ~D[2]; end
	3'b011: begin Y= D[3]; Ybar = ~D[3]; end
	3'b100: begin Y= D[4]; Ybar = ~D[4]; end
	3'b101: begin Y= D[5]; Ybar = ~D[5]; end
	3'b110: begin Y= D[6]; Ybar = ~D[6]; end
	3'b111: begin Y= D[7]; Ybar = ~D[7]; end
	default: begin Y= 1’b0; Ybar = 1’b1; end
	endcase
	else
	begin Y= 1’b0; Ybar = 1’b1; end
	end
	endmodule

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 1x4 Demultiplexer - 74x155 :

	module dualdemux(A,B,G1,C1,G2,C2,Y1,Y2);
	input A,B,G1,C1,G2,C2;
	output [0:3] Y1,Y2;
	assign Y1[0] = ~(~B & ~A & ~G1 & C1),
	Y1[1] = ~(~B & A & ~G1 & C1),
	Y1[2] = ~(B & ~A & ~G1 & C1),
	Y1[3] = ~(B & A & ~G1 & C1);
	assign Y2[0] = ~(~B & ~A & ~G2 & ~C2),
	Y2[1] = ~(~B & A & ~G2 & ~C2),
	Y2[2] = ~(B & ~A & ~G2 & ~C2),
	Y2[3] = ~(B & A & ~G2 & ~C2);
	endmodule

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