verilog code for 4-Bit Comparator - 74x85

 Code:

	module four_bit_comparator(A,B,AGBin,ALBin,AEQBin,AGBout,ALBout,AEQBout);
	input [3:0] A, B;
	input AGBin, ALBin,AEQBin;
	output reg AGBout,ALBout,AEQBout;
	always@(*)
	if(A > B)
	begin
	AGBout = 1;
	ALBout = 0;
	AEQBout = 0;
	end
	else if (A < B)
	begin
	AGBout = 0;
	ALBout = 1;
	AEQBout = 0;
	end
	else if (A == B)
	if (~AGBin & ~ALBin & ~AEQBin)
	begin
	AGBout = 1;
	ALBout = 1;
	AEQBout = 0;
	end
	else if (AGBin & ALBin & ~ AEQBin)
	begin
	AGBout = 0;
	ALBout = 0;
	AEQBout = 0;
	end
	else if (AEQBin)
	begin
	AGBout = 0;
	ALBout = 0;
	AEQBout = 1;
	end
	else
	begin
	AGBout = AGBin;
	ALBout = ALBin;
	AEQBout = AEQBin;
	end
	endmodule

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