Verilog Code for AND Logic Gate

AND Logic Gate

The Logic AND Gate is a digital logic circuit whose output goes HIGH to a logic level 1 only when all of its inputs are HIGH.

Gate Level Modeling

	module and_gate(A, B, Y);
	input A, B;
	output Y;
	and (Y, A, B);
	endmodule

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Data Flow Modeling

	module and_data(A, B, Y);
	input A, B;
	output Y;
	assign Y = A & B;
	endmodule

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Behavioral Modeling

	module and_beh(A, B, Y);
	input A, B;
	output reg Y;
	always@(A, B):
	begin
	if (A==1'b1 & B==1'b1)
	Y = 1'b1;
	else
	Y = 1'b0;
	end
	endmodule

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Test Bench

	module and_test;
	reg A, B;
	wire Y;
	and_gate and_test(A, B, Y);
	initial
	begin
	#000 A=0;B=0;
	#100 A=0;B=1;
	#100 A=1;B=0;
	#100 A=1;B=1;
	end
	initial
	begin
	$monitor($time,"A=%b,B=%b,Y=%b",A, B, Y);
	end
	endmodule

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TestBench Output: