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| module dflipflop(PR1,CLR1,D1,CLK1,PR2,CLR2,D2,CLK2,Q1,Q1bar,Q2,Q2bar); | |
| input PR1,CLR1,D1,CLK1,PR2,CLR2,D2,CLK2; | |
| output reg Q1, Q2; | |
| output Q1bar, Q2bar; | |
| assign Q1bar = ~Q1; | |
| assign Q2bar = ~Q2; | |
| always@(posedge CLK1, negedge CLR1, negedge PR1) | |
| begin | |
| if (PR1 == 0 && CLR1 == 1) | |
| Q1 = 1; | |
| else if (PR1 == 1 && CLR1 == 0) | |
| Q1 = 0; | |
| else if (PR1 == 1 && CLR1 == 1) | |
| Q1 = D1; | |
| else | |
| Q1 = Q1; | |
| end | |
| always@(posedge CLK2, negedge CLR2, negedge PR2) | |
| begin | |
| if (PR2 == 0 && CLR2 == 1) | |
| Q2 = 1; | |
| else if (PR2 == 1 && CLR2 == 0) | |
| Q2 = 0; | |
| else if (PR2 == 1 && CLR2 == 1) | |
| Q2 = D2; | |
| else | |
| Q2 = Q2; | |
| end | |
| endmodule |
